fpga乙個引腳控制喇叭發聲 25mhz
專案一、發出乙個單音 嗶嗶
module music(clk, speaker);
input clk;
output speaker;
// 16位計數
reg [15:0] counter;
always @(posedge clk) counter <= counter+1;
//計數器高位設定喇叭
assign speaker = counter[15];
endmodule
專案二：設定發出固定頻率440hz聲音
「a」音符（440hz） 時鐘週期25000000/440=56818
56818/2=28408
module music(clk, speaker);
input clk;
output speaker;
reg [14:0] counter;
always @(posedge clk) if(counter==28408) counter<=0; else counter <= counter+1;
reg speaker;
always @(posedge clk) if(counter==28408) speaker <= ~speaker;
endmodule
公升級module music(clk, speaker);
input clk;
output speaker;
parameter clkdivider = 25000000/440/2;
reg [14:0] counter;
always @(posedge clk) if(counter==0) counter <= clkdivider-1; else counter <= counter-1;
reg speaker;
always @(posedge clk) if(counter==0) speaker <= ~speaker;
endmodule
專案三、兩個音交替切換
module music(clk, speaker);
input clk;
output speaker;
parameter clkdivider = 25000000/440/2;
reg [23:0] tone;
always @(posedge clk) tone <= tone+1;
reg [14:0] counter;
always @(posedge clk) if(counter==0) counter <= (tone[23] ? clkdivider-1 : clkdivider/2-1); else counter <= counter-1;
reg speaker;
always @(posedge clk) if(counter==0) speaker <= ~speaker;
endmodule
專案四、警笛音
module music(clk, speaker);
input clk;
output speaker;
reg [22:0] tone;
always @(posedge clk) tone <= tone+1;
wire [6:0] ramp = (tone[22] ? tone[21:15] : ~tone[21:15]);
wire [14:0] clkdivider = ;
reg [14:0] counter;
always @(posedge clk) if(counter==0) counter <= clkdivider; else counter <= counter-1;
reg speaker;
always @(posedge clk) if(counter==0) speaker <= ~speaker;
endmodule
專案五、完整警笛音
module music(clk, speaker);
input clk;
output speaker;
reg [27:0] tone;
always @(posedge clk) tone <= tone+1;
wire [6:0] fastsweep = (tone[22] ? tone[21:15] : ~tone[21:15]);
wire [6:0] slowsweep = (tone[25] ? tone[24:18] : ~tone[24:18]);
wire [14:0] clkdivider = ;
reg [14:0] counter;
always @(posedge clk) if(counter==0) counter <= clkdivider; else counter <= counter-1;
reg speaker;
always @(posedge clk) if(counter==0) speaker <= ~speaker;
endmodule
always @(posedge clk) if(counter_note==0) counter_note <= clkdivider; else counter_note <= counter_note-1;
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