10.1 非流水線方式的8位全加器
///module adder8(cout,sum,ina,inb,cin,clk);
output cout;
reg cout;
output [7:0] sum;
reg [7:0] sum;
input [7:0] ina,inb;
input cin;
reg [7:0] tempa,tempb;
reg tempc;
always @ (posedge clk)
begin
tempa=ina;tempb=inb;tempc=cin;
endalways @ (posedge clk)
begin
assign =tempa+tempb+tempc;
endendmodule
10.2 4級流水線方式的8位全加器
/// module pipeline(cout,sum,ina,inb,cin,clk);
output [7:0] sum;
output cout;
input [7:0] ina,inb;
input cin,clk;
reg [7:0] tempa,tempb,sum;
reg tempci,firstco,secodeco,thirdco,cout;
reg [1:0] firsts,thirda,thridb;
reg [3:0] seconds,seconda,secondb;
reg [5:0] thirds,firsta,firstb;
always @ (posedge clk)
begin
tempa=ina;tempb=inb;tempci=cin;
endalways @ (posedge clk)
begin
=tempa[1:0]+tempb[1:0]+tempci;
firsta=tempa[7:2];
firstb=tempb[7:2];
endalways @ (posedge clk)
begin
=;seconda=firsta[5:2];
secondb=firstb[5:2];
endalways @ (posedge clk)
begin
=;thirda=seconda[3:2];
thirdb=secondb[3:2];
endalways @ (posedge clk)
begin
=;end
endmodule
10.3 兩個加法器和乙個選擇器的實現方式
/// module resource1(sum,a,b,c,d,sel);
parameter size=4;
output [size:0] sum;
reg [size:0] sum;
input [size-1:0]a,b,c,d;
input sel;
always @ ( a or b or c or d or sel)
begin
if (sel) sum=a+b;
else sum=c+d;
endendmodule
10.4 兩個選擇器和乙個加法器的實現方式
/// module resource2(sum,a,b,c,d,sel);
parameter size=4;
output [size:0] sum;
reg [size:0] sum;
input [size-1:0] a,b,c,d;
input sel;
reg [size-1:0] atemp,btemp;
always @ (a or b or c or d or sel)
begin
if (sel)
begin
atemp=a;
btemp=b;
endelse
begin
atemp=c;
btemp=d;
endsum=atemp+btemp;
endendmodule
10.5 狀態機設計的例子
///module fsm(clk,clr,out,start,step2,step3);
input clk,clr,start,step2,step3;
output [2:0] out;
reg [2:0] out;
reg [1:0] state,next_state;
parameter state0=2'b00,state1=2'b01,
state2=2'b11,state3=2'b10;
always @ (posedge clk or posedge clr)
begin
if(clr) state<=state0;
else state<=next_state;
endalways @ (state or start or step2 or step3)
begin
case(state)
state0: if(start) next_state<=state1;
else next_state<=state0;
state1: next_state<=state2;
state2: if(step2) next_state<=state3;
else next_state<=state0;
state3: if(step3) next_state<=state0;
else next_state<=state3;
default: next_state<=state0;
endcase
endalways @ (state)
begin
case(state)
state0:out=3'b001;
state1:out=3'b010;
state2:out=3'b100;
state3:out=3'b111;
default:out=3'b001;
endcase
endendmodule
10.6 自動轉換量程頻率計控制器
///module control(std_f_sel,reset,clk,clear,cntover,cntlow);
output [1:0] std_f_sel;
output reset;
input clk,clear,cntover,cntlow;
reg [1:0] std_f_sel;
reg reset;
reg [5:0] present,next;
parameter start_f100k=6'b000001,
f100k_cnt=6'b000010,
start_f10k=6'b000100,
f10k_cnt=6'b001000,
start_f1k=6'b010000,
f1k_cnt=6'b100000;
always @ (posedge clk or posedge clear)
begin
if(clear) present<=start_f10k;
else present<=next;
endalways @ (present or cntover or cntlow)
begin
case(present)
start_f100k: next<=f100k_cnt;
f100k_cnt: if(cntlow) next<=start_f10k;
else next<=f100k_cnt;
start_f10k:next<=f10k_cnt;
f10k_cnt: if(cntlow) next<=start_f1k;
else if(cntover) next<=start_f100k;
else next<=f10k_cnt;
start_f1k: next<=f1k_cnt;
f1k_cnt: if(cntover) next<=start_f10k;
else next<=f1k_cnt;
default: next<=start_f10k;
endcase
endalways @ (present)
begin
case(presetn)
start_f100k: begin reset=1; std_f_sel=2'b00; end
f100k_cnt: begin reset=0; std_f_sel=2'b00; end
start_f10k: begin reset=1; std_f_sel=2'b01; end
f10k_cnt: begin reset=0; std_f_sel=2'b01; end
start_f1k: begin reset=1; std_f_sel=2'b11; end
f1k_cnt: begin reset=0; std_f_sel=2'b11; end
default: begin reset=1; std_f_sel=2'b01; end
endcase
endendmodule
10.7 8位全加器
///module add8(sum,cout,a,b,cin);
output [7:0] sum;
reg [7:0] sum;
output cout;
input [7:0] a,b;
input cin;
assign =a+b+cin;
endmodule
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