使用工具：xilinx ise 14.7
7段解碼器主要是由七段解碼管組成，通過控制各個解碼管的開與關達到顯示出16進製制數的16個數。實現過程和3-8解碼器差不多，主要是構建乙個真值表作為map，然後一一對應就行了，**如下：
module code(
input wire [3:0] in,//輸入的數字
output reg [6:0] led,//7段解碼管的對映
output reg [3:0] en//顯示數字的位置，比如7為3'b111那麼在前三位都顯示7
);always @ (*)
case(in)
4'b0000: begin
led = 7'b1000000; en = 4'b1110;//0
end 4'b0001: begin
led = 7'b1111001; en = 4'b1110;//1
end 4'b0010: begin
led = 7'b0100100; en = 4'b1101;//2
end 4'b0011: begin
led = 7'b0110000; en = 4'b1100;//3
end 4'b0100: begin
led = 7'b0011001; en = 4'b1011;//4
end 4'b0101: begin
led = 7'b0010010; en = 4'b1010;//5
end 4'b0110: begin
led = 7'b0000010; en = 4'b1001;//6
end 4'b0111: begin
led = 7'b1111000; en = 4'b1000;//7
end 4'b1000: begin
led = 7'b0000000; en = 4'b0111;//8
end 4'b1001: begin
led = 7'b0010000; en = 4'b0110;//9
end 4'b1010: begin
led = 7'b0001000; en = 4'b0101;//a
end 4'b1011: begin
led = 7'b0000011; en = 4'b0100;//b
end 4'b1100: begin
led = 7'b1000110; en = 4'b0011;//c
end 4'b1101: begin
led = 7'b0100001; en = 4'b0010;//d
end 4'b1110: begin
led = 7'b0000110; en = 4'b0001;//e
end 4'b1111: begin
led = 7'b0001110; en = 4'b0000;//f
end endcase
endmodule
`timescale 1ns / 1ps
// company:
// engineer:
//// create date: 16:20:01 11/06/2014
// design name: code
// module name: c:/documents and settings/lab2/test.v
// project name: lab2
// target device:
// tool versions:
// description:
//// verilog test fixture created by ise for module: code
//// dependencies:
// // revision:
// revision 0.01 - file created
// additional comments:
// module test;
// inputs
reg [3:0] in;
// outputs
wire [6:0] led;
wire [3:0] en;
// instantiate the unit under test (uut)
code uut (
.in(in),
.led(led),
.en(en)
); initial begin
// initialize inputs
in = 0;
// wait 100 ns for global reset to finish
#50;
in = 2;
#50;
in = 3;
#50;
in = 4;
#50;
in = 5;
#50;
in = 6;
#50;
in = 7;
#50;
in = 8;
#50;
in = 9;
#50;
in = 10;
#50;
in = 11;
#50;
in = 12;
#50;
in = 13;
#50;
in = 14;
#50;
in = 15;
#50;
// add stimulus here
endendmodule
很難看懂是吧，在這裡附上開發板的實際效果圖與引腳檔案的編寫（我用的是nexys 3 ——spartan6 xc6lx16-cs324開發板）
net "in[3]" loc = "t5";
net "in[2]" loc = "v8";
net "in[1]" loc = "u8";
net "in[0]" loc = "n8";
net "en[3]" loc = "p17";
net "en[2]" loc = "p18";
net "en[1]" loc = "n15";
net "en[0]" loc = "n16";
net "led[6]" loc = "l14";
net "led[5]" loc = "n14";
net "led[4]" loc = "m14";
net "led[3]" loc = "u18";
net "led[2]" loc = "u17";
net "led[1]" loc = "t18";
net "led[0]" loc = "t17";
注意：在控制7段解碼管時0表示亮，1表示滅
Verilog 實現74138解碼器
首先明確有哪些輸入和輸出 enable 使能 en0 en1 en2 input 輸入 i0 i1 i2 output 輸出 o0 o7 然後把資料型別用verilog實現 使能端為三個 只有當使能為1 0 0的時候晶元才正常解碼 input wire 2 0 en 輸入端為三個二進位制位，對應2 ...
Verilog設計解碼器 計數器
實驗1 設計4 16解碼器 1.module decoder4 16a out,in output 15 0 out input 3 0 in reg 15 0 out out為16位暫存器 always in 迴圈輸入 begin case in 輸入4位十進位制數，輸出16位二進位制數 4 d0...
Verilog實現三八解碼器轉四 十六解碼器
用verilog實現三八解碼器 module decoder data out,en,data in input 2 0 data in input en output reg 7 0 data out always en or data in begin if en 1 case data in ...