用verilog 蜂鳴器的演奏樂曲

2021-10-07 10:09:41 字數 2905 閱讀 1976

module	song

(clk,beep)

;//模組名稱song

input clk;

//系統時鐘50mhz

output beep;

//蜂鳴器輸出端

reg beep_r;

//暫存器

reg[7:

0] state;

//樂譜狀態機

reg[16:

0]count,count_end;

reg[23:

0]count1;

//樂譜引數:d=f/2k (d:引數,f:時鐘頻率,k:音高頻率)

parameter l_3 =

17'd75850,

//低音3

l_5 =

17'd63776,

//低音5

l_6 =

17'd56818,

//低音6

l_7 =

17'd50618,

//低音7

m_1 =

17'd47774,

//中音1

m_2 =

17'd42568,

//中音2

m_3 =

17'd37919,

//中音3

m_5 =

17'd31888,

//中音5

m_6 =

17'd28409,

//中音6

h_1 =

17'd23889;

//高音1

parameter time =

12000000

;//控制每乙個音的長短(250ms)

assign beep = beep_r;

//輸出**

always@(posedge clk) begin

count <= count +

1'b1;

//計數器加1

if(count == count_end) begin

count <=

17'h0;

//計數器清零

beep_r <=

!beep_r;

//輸出取反

endend//曲譜 產生分頻的係數並描述出曲譜

always @(posedge clk) begin

if(count1 < time)

//乙個節拍250ms

count1 = count1 +

1'b1;

else begin

count1 =

24'd0;

if(state ==

8'd63)

state =

8'd0;

else

state = state +

1'b1;

case

(state)

8'd0:count_end = l_6;

8'd1:count_end=m_1;

8'd2:count_end=m_3;

8'd3:count_end=m_5;

8'd4,8'd5:count_end=m_3;

8'd6:count_end=m_3;

8'd7:count_end=m_2;

8'd8,8'd9:count_end=m_3;

8'd10:count_end=m_3;

8'd11:count_end=m_2;

8'd12,8'd13:count_end=m_3;

8'd14:count_end=l_6;

8'd15:count_end=l_7;

8'd16:count_end=m_1;

8'd17:count_end=m_3;

8'd18:count_end=m_2;

8'd19:count_end=m_1;

8'd20,8'd21:count_end=l_6;

8'd22,8'd23:count_end=l_5;

8'd24,8'd25,

8'd26,8'd27,

8'd28,8'd29,

8'd30,8'd31:count_end=l_3;

8'd32:count_end = l_6;

8'd33:count_end=m_1;

8'd34:count_end=m_3;

8'd35:count_end=m_5;

8'd36,8'd37:count_end=m_3;

8'd38:count_end=m_3;

8'd39:count_end=m_2;

8'd40,8'd41:count_end=m_3;

8'd42:count_end=m_3;

8'd43:count_end=m_2;

8'd44,8'd45:count_end=m_3;

8'd46:count_end=l_6;

8'd47:count_end=l_7;

8'd48:count_end=m_1;

8'd49:count_end=m_3;

8'd50:count_end=m_2;

8'd51:count_end=m_1;

8'd52,8'd53:count_end=l_6;

8'd54,8'd55:count_end=l_5;

8'd56,8'd57,

8'd58,8'd59,

8'd60,8'd61:count_end=l_6;

8'd62:count_end=l_6;

8'd63:count_end=l_7;

default

: count_end =

16'h0;

endcase

endendendmodule

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