使用pwm技術實現呼吸燈。利用占空比每1ms遞增1us的占空比來點亮led。沒隔1s實現燈由逐漸變亮到逐漸變暗，或者逐漸變暗到逐漸變數的轉換。使用的語言是verilog。
module led_breath
//#(
// parameter led_width = 4
//) (
input clk, //global clock
input rst_n, //global reset
output led_data );
//-----------------------------------
//counter for 1us
localparam t1us = 6'd100;
//localparam t1us = 6'd5; //just for simulation
reg [5:0] delay_1us_cnt;
always @ ( posedge clk or posedge rst_n )
begin
if ( rst_n )
delay_1us_cnt <= 6'd0;
else if ( delay_1us_cnt < t1us )
delay_1us_cnt <= delay_1us_cnt + 1'b1;
else
delay_1us_cnt <= 6'd1;
endwire delay_1us = ( delay_1us_cnt == t1us ) ? 1'b1 : 1'b0;
//-----------------------------------
//counter for 1ms
localparam t1ms = 10'd1000;
//localparam t1ms = 10'd100; //just for simulation
reg [9:0] delay_1ms_cnt;
always @ ( posedge clk or posedge rst_n )
begin
if ( rst_n )
delay_1ms_cnt <= 10'd0;
else if ( delay_1us )
delay_1ms_cnt <= ( delay_1ms_cnt < t1ms ) ? ( delay_1ms_cnt + 1'b1 ) : 10'd1;
else
delay_1ms_cnt <= delay_1ms_cnt;
endwire delay_1ms = ( delay_1ms_cnt == t1ms && delay_1us ) ? 1'b1 : 1'b0;
//-----------------------------------
//counter for 1s
localparam t1s = 10'd1000;
//localparam t1s = 10'd100; //just for simulation
reg [9:0] delay_1s_cnt;
always @ ( posedge clk or posedge rst_n )
begin
if ( rst_n )
delay_1s_cnt <= 10'd0;
else if ( delay_1ms )
delay_1s_cnt <= ( delay_1s_cnt < t1s ) ? ( delay_1s_cnt + 1'b1 ) : 10'd1;
else
delay_1s_cnt <= delay_1s_cnt;
endwire delay_1s = ( delay_1s_cnt == t1s && delay_1ms ) ? 1'b1 : 1'b0;
//-----------------------------------
//pwm parameter
wire [9:0] duty_cnt = delay_1ms_cnt;
wire [9:0] period_cnt = delay_1s_cnt;
//-----------------------------------
//switch mode
reg display_mode;
always @ ( posedge clk or posedge rst_n )
begin
if ( rst_n )
display_mode <= 1'b0;
else if ( delay_1s )
display_mode <= ~ display_mode;
else
display_mode <= display_mode;
end//-----------------------------------
//generate pwm
reg pwm_on;
always @ ( posedge clk or posedge rst_n )
begin
if ( rst_n )
pwm_on <= 1'b0;
else
case ( display_mode )
1'b0: pwm_on <= ( duty_cnt < period_cnt ) ? 1'b1 : 1'b0;
1'b1: pwm_on <= ( duty_cnt < period_cnt ) ? 1'b0 : 1'b1;
default:;
endcase
end//-----------------------------------
//output to led
assign led_data = pwm_on;
endmodule
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